Semiconductor shape and placement metrology is challenged by constantly changing conditions in the characteristics of the wafer to be measured. Although it is the objective of all advanced process control methodologies to keep all manufacturing conditions stable with minimal temporal and spatial variation, this objective is in practice unattainable. Semiconductor processes performed by semiconductor process tools (e.g. lithographic tools, deposition tools, etch tools, polish tools, and the like) may drift over time, resulting in corresponding variations of the target wafer characteristics such as, but not limited to, composition, film thickness, feature size, or optical characteristics across the wafer or lot of wafers. These variations of target wafer characteristics may have a detrimental impact on subsequent metrology steps. For example, a film thickness variation of a particular layer across the wafer may result in varying accuracy or precision performance when an overlay metrology measurement is performed. Although targets may be designed for their robustness in the face of such variations, the range of tolerable variations to maintain tolerable metrology performance is bounded. If the variations extend beyond these bounds, a metrology performance excursion results, with a potential negative impact on the process control.